1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, it relates to a power supply system for use in a semiconductor integrated circuit with large power consumption such as a system LSI.
2. Description of the Related Art
In recent years, in semiconductor integrated circuits such as system LSIs, high integration of transistors has progressed, and voltage drop caused by resistance of power wiring lines formed in the state of multiple layers is no longer negligible. In such semiconductor integrated circuits, a power is supplied from power wiring lines in an upper layer connected to power pins to power wiring lines (hereinafter referred to as “the cell power wiring lines”) for functional cells (e.g., an AND gate and an OR gate) for realizing a predetermined electric function formed in lower layers. Here, in the power supply system, the power wiring lines are formed in the state of multiple layers and in a grid state, and a grid-like power voltage structure for supplying a power is used (e.g., see Jpn. Pat. Appln. KOKAI Publication No. 2000-11011).
In the system that the power is supplied from the upper layer power wiring lines to the cell power wiring lines via the plural grid-like power wiring lines described above, the power wiring lines having large widths can be used in the upper layer, but the power wiring lines having small widths can only be used for the lower layers as they go down. In consequence, there arises a problem that voltage drop by the power wiring lines becomes larger. To prevent this problem, spaces between the power wiring lines formed in the lower layers must be decreased to increase the power wiring lines. In the lower layers, however, the same wiring line layers are used for the power wiring lines and ordinary wiring lines. Therefore, when the spaces between the power wiring lines are decreased to increase the power wiring lines, there is a problem that regions available for the ordinary wiring lines decrease.